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INTEGRATED CIRCUITS
DATA SHEET
SAA7282 Terrestrial Digital Sound Decoder (TDSD2)
Product specification File under Integrated Circuits, IC02 July 1993
Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
FEATURES * Full EBU NICAM 728 specification decoder * Microcomputer controlled via I2C-bus * Automatic decoding and output configuration depending upon transmission: - digital stereo - digital mono and data - 2 independent mono signals * On board RAM for de-interleaving and 10 to 14-bit word expansion * Automatic mute function which silences the digital data and switches to FM sound (if valid) when error rate exceeds user definable limit * User mute function (MUTE pin) to enable user to perform muting to their own software algorithm if required, or to simply silence the output * 4 times over-sampling digital filter * Selectable digital de-emphasis * 256 times over-sampling Noise Shapers * Fully integrated 1-bit DACs * Integrated switching networks allowing selection between NICAM Sound, FM Sound or external "Daisy-Chain" input * Digital Audio Interface conforming with EBU/IEC 958 * I2C-bus transceiver enabling a master device to read - status information QUICK REFERENCE DATA SYMBOL VDD IDD fXTAL Tamb supply current crystal frequency operating ambient temperature PARAMETER positive supply voltage 4.5 - - 0 MIN. 5.0 50 8.192 - TYP. 5.5 100 - 70 MAX. GENERAL DESCRIPTION - error count byte - additional data bits and write: - switch control codes - decoder control - upper and lower error rate limits. APPLICATIONS * Television receivers * Video cassette recorders.
SAA7282
Performing all digital decoding functions for a NICAM 728 digital stereo sound system, the SAA7282 is a highly integrated CMOS circuit which only requires a DQPSK (Differential Quadrature Phase Shift Keying) demodulator (TDA8732) and minimum external components to achieve a full NICAM solution. The device may also be interfaced to other DQPSK demodulators.
UNIT V mA MHz C
ORDERING INFORMATION EXTENDED TYPE NUMBER SAA7282ZP SAA7282GP Note 1. SAA7282ZP: 32-DIL32SHR; plastic (SOT232A); SOT232-1; 1996 November 28. 2. SAA7282GP: 44-QFP; plastic (SOT205AG); SOT205-1; 1996 November 28. July 1993 2 PACKAGE PINS 32 44 PIN POSITION DIL32SHR QFP MATERIAL plastic plastic CODE SOT232A(1) SOT205AG(2)
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SCL SDA ADSEL 3 5
2
Philips Semiconductors
Terrestrial Digital Sound Decoder (TDSD2)
VDAC 18
CDL 19
INTL 20 VRC 25 24 23
4
6
V DDAL VSSAL OPL
PORT2
IC
1-BIT DAC
2 RESET AUTO MUTE NICAM 728 DECODING
SAA7282ZP
NOISE SHAPER 21 22 10 DIGITAL SWITCHING FILTER DE-EMPH BIAS 11 13 FML EXTL VRO VRC EXTR FMR
DATA
32
handbook, full pagewidth
3
26 i.c. VDD VSS 27 29 FREQ. SYNTH. XTAL OSC
DIGITAL AUDIO INTERFACE
NOISE SHAPER
14
12 1-BIT DAC VRC 9 1 PCLK 30 XIN 31 7 28 DOBM 17 V REF 16 CDR 15
MLB152
OPR V DDAR V SSAR
8
XOUT MUTE
INTR
Product specification
SAA7282
Fig.1 Block diagram; pin numbering for SOT232A.
Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
PINNING SYMBOL SOT205AG DOBM VSS n.c. XIN XOUT DATA PCLK RESET SCL SDA PORT2 n.c. ADSEL MUTE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SOT232A 28 29 - 30 31 32 1 2 3 4 5 - 6 7 digital audio interface output ground connection for the digital section not connected crystal input at 256fs (8.192 MHz) crystal output at 256fs (8.192 MHz) serial data input at 728 kbits/s from DQPSK demodulator output clock at 728 kHz to DQPSK demodulator DESCRIPTION
SAA7282
active LOW reset; used to set the device in a valid initial condition clock input for I2C control bus data port for I2C control bus, input/open drain output output mirroring the I2C control register bit PORT2 not connected I2C-bus slave address selection input; allows selection of one of two separate slave addresses, defaults to logic 1 active LOW mute input; when set LOW, sets the digital data to zero and either silences the output or switches it to analog FM, depending on the status of MUTEDEF (control bit in the I2C register) and RSSF; overridden by automute (if automute is used, then MUTE is automatically pulled LOW) not connected analog supply voltage for the right audio channel analog ground connection for the right audio channel internal reference voltage buffer output internal reference voltage buffer HIGH impedance node not connected analog output from the right audio channel external analog input to the right audio channel FM sound input to the right audio channel integrator output from the right audio channel integrator connection to an external damping capacitor not connected reference voltage input; 2.5 V (typical) quiet VSS to DACs integrator connection to an external damping capacitor integrator output from the left audio channel FM sound input to the left audio channel external analog input to the left audio channel analog output from the left audio channel not connected analog ground connection for the left audio channel analog supply voltage for the left audio channel
n.c. VDDAR VSSAR VRO VRC n.c. OPR EXTR FMR INTR CDR n.c. VREF VDAC CDL INTL FML EXTL OPL n.c. VSSAL VDDAL
15 to 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
- 8 9 10 11 - 12 13 14 15 16 - 17 18 19 20 21 22 23 - 24 25
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
SYMBOL SOT205AG n.c. i.c. n.c. VDD 39 to 41 42 43 44
SOT232A - 26 - 27 not connected
DESCRIPTION internally connected; must be left open-circuit in application not connected digital supply voltage
handbook, halfpage
PCLK RESET SCL SDA PORT2 ADSEL MUTE VDDAR V SSAR
1 2 3 4 5 6 7 8 SAA7282ZP 9
32 DATA 31 XOUT 30 XIN 29 V SS 28 DOBM 27 VDD 26 i.c. 25 VDDAL 24 VSSAL 23 OPL 22 EXTL 21 FML 20 INTL 19 CDL 18 VDAC 17 VREF
MLB153
VRO 10 VRC 11
OPR 12 EXTR 13 FMR 14 INTR 15 CDR 16
Fig.2 Pin configuration (SOT232A).
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
38 VDDAL
37 VSSAL
handbook, full pagewidth
DOBM 1 V SS 2 n.c. 3 XIN 4 XOUT 5 DATA 6 PCLK 7 RESET 8 SCL 9 SDA 10 PORT2 11 SAA7282GP
34 EXTL
44 VDD
35 OPL
43 n.c.
41 n.c.
40 n.c.
39 n.c.
36 n.c.
42 i.c.
33 FML 32 INTL 31 CDL 30 V DAC 29 VREF 28 n.c. 27 CDR 26 INTR 25 FMR 24 EXTR 23 OPR
ADSEL 13
MUTE 14
VDDAR 18
V SSAR 19
VRO 20
VRC 21
n.c. 12
n.c. 15
n.c. 16
n.c. 17
n.c. 22
MLB154
Fig.3 Pin configuration (SOT205AG).
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
I2C-BUS FORMATS The SAA7282 contains an I2C-bus slave transceiver permitting a master device to: * Read decoder status information derived from the transmitted digital audio signal
SAA7282
* Read an error count byte to determine the bit error rate for user mute purposes and to indicate quality of NICAM signal * Read additional transmitted data bits. Their purpose has yet to be defined but accessibility is provided to allow future services to be implemented in receiver software * Write control codes to select the available analog switching configurations * Write upper and lower error count limits for automatic muting function The device slave address is A(7:1)(R/W) = 101101X(R/W). An ADSEL pin is provided to allow selection of one of two different slave addresses via programmable address bit A1. (X = ADSEL logic level). The SAA7282 does not acknowledge the I2C-bus general call address. The slave receiver format is: S SLAVE_ADDR.0 ACK SUB_ADDR ACK DATA BYTE ACK P <-n bytes-> Where S = start, ACK = acknowledge, P = stop. Auto-increment of the sub-address is provided with wrap-around from 02 (HEX) to 00 (HEX). The slave receiver data byte format, as a function of sub-address, is as shown in Table 1. Table 1 Slave receiver data byte. RESET VALUE HEX 90 50 14 D7 M1/M2 EMAX7 EMIN7 D6 DMSEL EMAX6 EMIN6 D5 SSWIT3 EMAX5 EMIN5 D4 SSWIT2 EMAX4 EMIN4 D3 SSWIT1 EMAX3 EMIN3 D2 PORT2 EMAX2 EMIN2 D1 MUTEDEF EMAX1 EMIN1 D0 AMDIS EMAX0 EMIN0
SUBADDRESS 00 01 10 M1/M2
This bit in conjunction with DMSEL bit, determines the output configuration in dual mono mode (see Table 2). Power-on resets to logic 1. DMSEL This bit determines whether one or both of the dual mono signals are output (see Table 2). Power-on resets to logic 0. PORT2 PORT2 controls a bit out, providing direct access to a dedicated output pin (PORT2) via the I2C-bus. See Table 3. Power-on resets to logic 0. SSWIT3/2/1 These bits control the analog switching, selecting between the FM, external, and NICAM signals. With the NICAM source the signals select whether the de-emphasis is performed and what gain is applied after the filtering and de-emphasis stage. The signal states and their meaning are listed in Table 4. Power-on resets to 0/1/0.
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
AMOGMDIS This bit enables and disables the automute function (which is activated according to the error limit registers). Power-on resets to enabled (i.e. AMDIS = logic 0). AMDIS should be disabled for the user definable mute (MUTE) to be used. MUTEDEF This defines the operation of the user definable MUTE pin when it is pulled LOW externally. If MUTEDEF is HIGH and RSSF = logic 1, the output of the device is switched to FM input. If MUTEDEF is HIGH and RSSF = logic 0, or if MUTEDEF is LOW, the output is muted. Power on resets to LOW. ERROR LIMIT REGISTERS UPPER ERROR LIMIT REGISTER
SAA7282
This defines the number of errors in 128 ms period which will cause automute to switch IN. User definable, but power on resets to 50 Hex. LOWER ERROR LIMIT REGISTER This defines the number of errors in 128 ms period which will cause automute to switch OUT. User definable, but power on resets to 14 Hex.
Table 2
Output as a function of M1/M2 and DMSEL. M1/M2 0 1 0 1 FUNCTION selects DIGITAL; L = M2, R = M2 selects DIGITAL; L = M1, R = M1 selects DIGITAL; L = M2, R = M1 selects DIGITAL; L = M1, R = M2
DMSEL 0 0 1 1 Table 3 Port 2 control. PORT2 0 1 Table 4
PIN OUTPUT STATE LOW HIGH
SSWIT signal states and function.(1) SSWIT2 0 0 1 1 x x SSWIT1 0 1 0 1 0 1 FUNCTION NICAM source de-emphasis switched out, no gain NICAM source de-emphasis switched in, no gain NICAM source de-emphasis switched in, -6 dB gain; power-on reset state NICAM source de-emphasis switched in, +12 dB gain external inputs switched in, no change to previous de-emphasis/gain setting FM inputs switched in, no change to previous de-emphasis/gain setting
SSWIT3 0 0 0 0 1 1 Note
1. Where x = don't care.
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
Slave Transmitter The slave transmitter formats are illustrated thus: * S SLAVE_ADDR.1 A STATUS_BYTE NA P In this format the bus master reads the STATUS_BYTE once. * S SLAVE_ADDR.1 A STATUS_BYTE A ERROR_BYTE NA P In this format the bus master reads two bytes of STATUS_BYTE and ERROR_BYTE. * S SLAVE_ADDR.1 A STATUS_BYTE A ERROR_BYTE A AD_BYTE_0 A AD_BYTE_1 NA P
SAA7282
In this format the bus master reads four bytes of STATUS_BYTE, ERROR BYTE and two additional bytes, AD_BYTE_0 and AD_BYTE_1. The additional data bytes contain the eleven additional data bits AD0 to AD10 together with information regarding their status. Where NA = no acknowledge. Table 5 Data byte formats. BYTE STATUS_BYTE ERROR_BYTE AD_BYTE_0 AD_BYTE_1 E7 AD7 OVW D7 PONRES E6 AD6 SAD D6 S/M E5 AD5 0 D5 D/S E4 AD4 CI2 D4 VDSP E3 AD3 CI1 D3 RSSF OS E2 AD2 AD10 D2 AM E1 AD1 AD9 D1 E0 AD0 AD8 D0 CFC
The bits may be defined as follows: PONRES This bit is a power-on reset detection bit. It is set HIGH after a power-on reset or supply reduction and is cleared LOW when the STATUS_BYTE is read. S/M (stereo/mono indication) S/M = logic 1 indicating an incoming stereo transmission. S/M = logic 0 indicating that the incoming transmission is not stereo. D/S (dual/single mono indication) D/S = logic 1 indicating an incoming dual mono transmission. D/S = logic 0 indicating that the incoming transmission is not dual mono. VDSP This bit indicates that the decoded signal is valid digital sound. When VDSP = logic 0 the incoming transmission carries either a 704 kbit/s transparent data channel or a currently undefined format and the device automatically switches to FM regardless of RSSF.
RSSF RSSF is the reserve sound switching flag indication equal to the C4 bit in the NICAM transmission. RSSF = logic 1 when the FM sound signal is carrying the same programme material as the digitally modulated carrier (specifically the M1 signal in the event of a dual mono transmission). RSSF = logic 0 when the FM signal is not reproduced within the digital signal. OS This bit provides an active LOW indication that the decoder is out of sync. If OS = logic 1 the decoder is frame synchronized and has obtained C0 (16 frame) sync. If OS = logic 0, the decoder is out of sync and the indicator bits are as given in Table 6. AM This bit indicates when the automuting function has switched from the NICAM sound to the conventional FM sound. This enables the software controller to display the relevant information to the customer, for example, on screen display. If AM bit = logic 0 no switching has been carried out by the automuting function. If AM bit = logic 1 then the automuting function has switched to the FM inputs.
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
CFC Signals a change of configuration at the 16-frame boundary. It is cleared to logic 1 by the I2C-bus reading the status register. E7 to E0 This is an error count byte which counts the number of error flags in a 128 ms period. The register is updated every 128 ms. AD10 to AD0 These are the additional data bits from the transmission and are updated every 1 ms.This provides a data capacity of 11 kbit/s. SAD SAD is the 'status additional data' bit. This is set to logic 1 when new bits AD10 to AD0 are latched into the I2C-bus registers. It is automatically reset to logic 0 when AD_BYTE_1 is read by the bus master. Table 6 Indicator bits functional truth table. TRANSMISSION Stereo M1 + M2 M1 + data Transparent data Decoder unsynchronized (OS = logic 0) Note C1 0 0 1 1 C2 0 1 0 1 C3 0 0 0 0 S/M 1 0 0 0 0 note 1 D/S 0 1 0 0 0 note 1 OVW
SAA7282
OVW is the overwrite indicator for the additional data. This bit is set when the transmission overwrites additional data bits which have not been read by the bus master. This bit is automatically reset to logic 0 when AD_BYTE_1 is read by the bus master. CI1 to CI2 These represent the CI bits which are extracted by a majority logic process from the parity checks of the last ten samples in a frame (samples 55 to 64). CI1 will be conveyed by the parity grouping of samples 55 to 59 and CI2 will be conducted by the parity grouping of samples 60 to 64. Both parity groups will be even for UK transmissions such that CI2 = logic 0 and CI1 = logic 0. The transmissions of countries following the specification issued by the EBU (Document SPB424; "Digital sound transmissions in terrestrial television") will allow odd or even parity groups, thus providing an additional 2 kbit/s data capacity.
VDSP 1 1 1 0 0 0
OS 1 1 1 1 1 0
Any currently undefined combination of C1, C2, C3
1. Holds last value before synchronization loss or stereo (S/M = logic 1; D/S = logic 0) if synchronization not achieved since power-on reset.
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
DIGITAL AUDIO INTERFACE IEC/EBU 958 Block structure The output is grouped into a block of 192 consecutive frames providing, for each channel the 192 channel status data bits. The start of a block is designated by a special sub-frame preamble. Frame structure Each frame is uniquely composed of two sub-frames. The rate of transmission of frames corresponds exactly to the source sampling frequency. In the 2-channel operation, samples taken from both channels are transmitted by time multiplexing in consecutive sub-frames. Sub-frames related to Channel 1 (left or 'A' channel in stereophonic operation and primary channel in monophonic operation) normally use preamble M. However the preamble is changed to preamble B once every 192 frames. This defines the block structure used to organize the channel status information. Sub-frames of Channel 2 (right or 'B' channel in stereophonic operation and secondary channel in monophonic operation) always use preamble W. Sub-frame structure
SAA7282
Each frame is divided into 32 time-slots numbered 0 to 31. Time-slots 0 to 3 carry one of three permitted preambles. These are used to affect synchronization of sub-frames, frames and blocks. Time-slots 4 to 27 carry the audio sample word in linear two's complement representation. The most significant bit is carried by time-slot 27. Time-slot 28 carries the validity flag associated with the audio sample word. This flag is set to logic 0 if the audio sample is reliable. If set to logic 1 then the sample is unreliable. Time-slot 29 carries one bit of the user data channel. In this application this is not used and so is set to logic 0. Time-slot 30 carries one bit of the channel status world associated with the audio channel transmitted in the same sub-frame. Time-slot 31 carries a parity bit such that time-slots 4 to 31 inclusive will carry an even number of ones and an even number of zeros.
handbook, full pagewidth
M
channel 1
W
channel 2
B
channel 1 sub-frame
W
channel 2 M
channel 1 W
channel 2
sub-frame frame 1
MLB155
frame 191
frame 0 start of block
Fig.4 Frame format.
0
handbook, full pagewidth
34 sync preamble
MLB156
11 12
L S B
27 28
M S B
31
logical 0 bits
audio sample word
VUCP
validity flag user data = logic 0 channel status parity bit
Fig.5 Sub-frame format.
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
Channel coding Time-slots are encoded as biphase mark data. Each bit transmitted is represented by a symbol comprising two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit being transmitted is logic 0, however it is different if the bit is logic 1 (see Table 7). Preambles
SAA7282
Preambles are specific patterns providing synchronization and identification of the sub-frames and blocks. A set of three preambles is used. These preambles are transmitted in the time allocated to four time-slots and are represented by eight successive states. The first state of the preamble is always different from the second state of the previous symbol. Depending on this state the preambles are as shown in Table 8. Table 8 Preambles. 0 11101000 11100010 11100100 1 00010111 00011101 00011011 Preamble B M W Channel coding
Table 7
Channel coding. 0 11 10 1 00 01 Channel coding
Preceding state Transmitted bit 0 1
Preceding state
The preambles preceding each digital audio sample are used to indicate the beginning of a sample as follows: * Preamble B indicates the start of Channel A data and the beginning of a block * Preamble M indicates the start of Channel A data but not the beginning of a block * Preamble W indicates the start of Channel B data. Channel status The channel status information is organized in 192-bit words. The first bit of each word is carried in the frame with Preamble B. The 192-bit word is organized into sections as shown in Table 9. Table 9 Channel status codes. BIT 0 1 2 3, 4 5 6, 7 8 to 15 16 to 19 20 to 23 24 to 27 28, 29 30 to 191 CODE 0 0 1 00 11 0 00 00110001 0000 0000 1100 00 all 0s category code source code (don't care) channel number (don't care) sampling frequency (32 kHz) clock accuracy (level II) consumer sound data digital copy permitted indicates digital de-emphasis switched in indicates digital de-emphasis switched out DESCRIPTION
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL VDD VI(max) VO(max) IIOK IO(max) Tamb Tstg Vstat Notes 1. All VDD and VSS connections must be made externally to the same power supply. PARAMETER supply voltage (all supplies) maximum input voltage (any input) maximum output voltage DC input or output diode current output current (each output) ambient operating temperature storage temperature electrostatic handling notes 2 and 3 CONDITIONS note 1 MIN. -0.5 -0.5 -0.3 - - 0 -55 -2000 MAX. +6.5 VDD+0.5 VDD+0.5 20 10 +70 +125 +2000
SAA7282
UNIT V V V mA mA C C V
2. Electrostatic handling is equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a 15 ns rise time. 3. 1000 V VSSAL pin.
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = 0 to +70 C; unless otherwise specified. SYMBOL Supplies VDD IDD supply voltage total supply current see Fig.9 4.5 - 0 see Fig.9 4.5 5.0 50 - 5.0 5.5 100 0 5.5 PARAMETER CONDITIONS MIN. TYP.
SAA7282
MAX.
UNIT
V mA V V
VSS,VSSAL ground supply voltage VSSAR,VDAC VDDAL, VDDAR DATA VIL VIH ILI CI VIL VIH ZI CI VIL VIH Vhys SCL VIL VIH Vhys ILI CI LOW level input voltage HIGH level input voltage hysteresis input leakage current input capacitance LOW level input voltage HIGH level input voltage input leakage current input capacitance LOW level input voltage HIGH level input voltage input impedance input capacitance LOW level input voltage HIGH level input voltage hysteresis analog supply voltage
Digital inputs 0 2.0 -10 - 0 2.0 - - 0 3.0 0.05VDD 0 3.0 0.05VDD -10 - - - - - - - 50 - - - - - - - - - 0.8 VDD +10 10 0.8 VDD - 10 1.5 VDD - 1.5 VDD - +10 10 V V A pF V V k pF V V V V V V A pF
ADSEL (this pin is internally pulled HIGH when not connected)
RESET (Schmitt trigger input)
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
SYMBOL Digital input/output SDA VIL VIH Vhys ILI CI VOL CL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LOW level input voltage HIGH level input voltage hysteresis input leakage current input capacitance LOW level output voltage load capacitance active pull-up passive pull-up IOL = 3 mA
0 3.0 0.05VDD -10 - 0 - - 0 2.0 - IOL = 2.8 mA 0 2.4 - -
- - - - - - - - - - - - - - 50
1.5 VDD - +10 10 0.4 400 200 0.8 VDD 10 0.4 VDD 50 -
V V V A pF V pF pF V V pF V V pF k
MUTE I/O (this pin has an internal pull-up) VIL VIH CI VOL VOH CL ZI LOW level input voltage HIGH level input voltage input capacitance LOW level output voltage HIGH level output voltage load capacitance input impedance
Digital outputs PORT2, PCLK, DOBM VOL VOH CL fc gm Av CI CFB CO XIN VIL VIH ILI CI LOW level input voltage HIGH level input voltage input leakage current input capacitance 0 3.5 -10 - - - - - 1 VDD +10 10 V V A pF LOW level output voltage HIGH level output voltage load capacitance IOL = 2.8 mA IOH = 800 A 0 2.4 - - at 100 kHz Av = gm.Ro 1.5 3.5 - - - - - - 0.4 VDD 50 - - - 10 5 10 V V pF
Crystal oscillator crystal frequency mutual conductance small signal gain input capacitance feedback capacitance output capacitance 8.192 - - - - - MHz mA/V V/V pF pF pF
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
SYMBOL
PARAMETER
CONDITIONS - at 0 Hz to 15 kHz at f 17 kHz - 30 -
MIN.
TYP. -
MAX.
UNIT
Digital filter specification fs PR SBA output sample frequency pass band ripple stop band attenuation 128 - - - kHz dB dB 0.01 - 0.09
Digital de-emphasis DEV deviation from ideal dB ANALOG SECTION (measured at VDD = 5 V and Tamb = 25 C) Reference voltage buffer VRC output Vrc DACs VREF input Vref CL RL ZO G PSRR Vain S/N THD CHM Vain THD+N CHM DIGS reference input voltage - - 3 - -0.35 - - FM or EXT FM or EXT FM or EXT, 1 kHz at 0 dB; VREF = 2.5 V NICAM 728; notes 2 and 3 0 dB, 1 kHz MUTE on 90 - - 0.9 - - - 0.5VDD - - 150 0 40 - 100 -90 0 1.0 -80 0 -80 - V Switching operational amplifiers output load capacitance output load resistance output impedance output gain power supply rejection ratio input voltage level (RMS value) signal-to-noise ratio (relative to 1 V RMS, unity gain) total harmonic distortion (unity gain, O/P = 1 V RMS) channel matching input voltage level (RMS value) total harmonic distortion plus noise channel matching digital silence level 300 - - +0.35 - 1.1 - -70 0.5 1.1 -75 0.5 - pF k dB dB V dB dB dB V dB dB dB voltage reference at VRC see Fig.10 0.45VDDAR 0.5VDDAR 0.55VDDAR V
External inputs selected (FML, FMR, EXTL, EXTR)
NICAM inputs selected (INTL, INTR)
Timing (all timing values refer to VIH and VIL levels) DATA with respect to PCLK (see Fig.7) tSU;DAT tHD;DAT data set-up time data hold time 100 250 - - - - ns ns
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - - - - - - - -
TYP.
MAX.
UNIT
SDA with respect to SCL (see Fig.8) fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tof Notes 1. Outputs OPL and OPR are measured with external components as recommended in Fig.11. 2. Total analog performance is limited by dynamic range of the NICAM 728 system. Due to compansion the quantization noise is never lower than approximately -62 dB with respect to the input level. 3. Measured with a -30 dB, 1 kHz NICAM 728 input signal. 4. Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL. 5. If a fast I2C-bus device is used in an up to 100 kbit/s I2C-bus system, then the requirement tSU;DAT 250 ns is always fulfilled if this device cannot stretch the LOW level of the SCL signal. If a device stretches the LOW level of the SCL signal, then data to SD9A must be asserted (tRD(max) + tSU;DAT) = 1000 + 250 = 1250 ns before the SCL signal is released to be compatible with the up to 100 kbit/s I2C-bus specification. 6. The output fall time is measured between 3.0 V and 1.5 V for a bus capacitance of 400 pF and an active pull-up. SCL clock frequency bus free time start code hold time SCL clock LOW time SCL clock HIGH time start code set-up time data hold time data set-up time SDA and SCL rise time SDA and SCL fall time stop code set-up time output fall time note 6 note 4 note 5 0 1300 600 1300 600 600 0 100 50 50 600 50 400 - - - - - - - 300 300 - 200 kHz ns ns ns ns ns ns ns ns ns ns ns
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
UHF handbook, full pagewidth INPUT TUNER
SAW FILTER VISION IF DEMODULATOR (TDA3852) COMPOSITE VIDEO DOBM I2 C-bus EXTL EXTR
DAI
I 2C AUDIO O/P R FILTER DAC + SWITCHES
8.192 MHz AUTO - MUTE
6 MHz (I)
NICAM DECODER
AUDIO O/P L
SAA7282
5.5 MHz (B/G) 6.552 MHz (I) SOUND DEMODULATOR (TDA3857) 5.85 MHz (B/G) ANALOG FM SOUND
MLB157
DATA
PCLK
FML
FMR
PHILIPS DQPSK DEMODULATOR (TDA8732) NIDEM
13.104 MHz (I) 11.7 MHz (B/G)
Fig.6 System block diagram showing SAA7282 with TDA8732.
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Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
handbook, full pagewidth
PCLK
DATA
MLB158
t SU;DAT
t HD;DAT
Fig.7 Data output timing.
t BUF
handbook, full pagewidth
t CYC
SDA t HD;STA tr tf t HD;STA
SCL t SU;STA Sr REPEATED START CONDITION t SU;STO P
P
S
t LOW
t HD;DAT t HIGH
t SU;DAT
STOP START CONDITION CONDITION
MLA396 - 1
Fig.8 I2C-bus interface timing.
July 1993
19
Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
handbook, full pagewidth
supply 10 22 22
100 nF
47 F
100 nF
47 F
VDDAR 8 25
V DDAL 27
VDD
MEA257 - 1
SAA7282ZP
Fig.9 VDD external circuitry.
10
handbook, full pagewidth
supply 100 nF 47 F V DDAR 8 11 VRC 100 nF SAA7282ZP 47 F
MEA256 - 1
Fig.10 VRC external circuitry (same external circuit values also required for VRO).
July 1993
20
Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
handbook, full pagewidth
51 k 330 pF VREF 68 pF CDL 19 220 nF INTL 20 EXTL 22 220 nF FML 21
23
OPL
MLB159
VRC
VRC
SAA7282ZP
Fig.11 External circuitry for left channel DAC (same external circuit values also required for right channel DAC).
July 1993
21
Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
PACKAGE OUTLINES SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
SAA7282
SOT232-1
D seating plane
ME
A2 A
L
A1 c Z e b 32 17 b1 wM (e 1) MH
pin 1 index E
1
16
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
July 1993
22
Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SAA7282
QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SOT205-1
c
y X
33 34
23 22 ZE
A
e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L Lp A A2 A1 (A 3)
e
vM A
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
July 1993
23
Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. QFP REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). July 1993 24
SAA7282
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 C. WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Product specification
Terrestrial Digital Sound Decoder (TDSD2)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7282
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
July 1993
25

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